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FMS9884A
Graphics Digitizer
3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps Features
* * * * * * * 3-channels 100/140/175 Ms/s conversion rate Programmable Clamps Adjustable Gain and offset Internal Reference Voltage I2C/SMBus compatible Serial Port Pin Compatible with AD9884A is via registers, accessible through an SMBus/I2C compatible serial port. Input amplitude range is 500-1000mV with either DC or AC coupling. Lower reference of AC coupled inputs is established with input clamps that are either internally generated or externally provided. Common to the three channels are clamp pulses, a bandgap reference voltage and clocks derived from a PLL or an external source. Digital data levels are 2.5-3.3 volt CMOS compliant. Power can be derived from a single +3.3 Volt power supply. For 175 MHz applications see special VPLL requirements. Package is a 128-lead MQFP. Performance specifications are guaranteed over 0C to 70C range. Product Number FMS9884AKAC100 FMS9884AKAC140 FMS9884AKAC175 Speed 108 Ms/s 140 Ms/s 175 Ms/s
Applications
* Flat panel displays and projectors * RGB Graphics Processing
Description
As a fully integrated analog interface, the FMS9884A can digitize RGB graphics with resolutions up to 1600 x 1200/65Hz refresh or 1600 x 1200/85Hz using alternate pixel sampling. ADC sampling clock can be derived from either an external source or incoming horizontal sync signal using the internal PLL. Output data is released through either one port at full rate or both ports, each running at half-rate. Setup and control
Block Diagram
Gain & Offset A/D Converter RPD7-0 Switch DRB7-0 GPD7-0 Switch DRA7-0
RIN
Clamp
GIN
Clamp
Gain & Offset
A/D Converter
DGA7-0 DGB7-0
BIN
Clamp
Gain & Offset
A/D Converter
BPD7-0 Switch
DBA7-0 DBB7-0
VREFIN CLAMP INVSCK XCK HSIN COAST LPF SDA SCL A0 A1 PWRDN HS PLL PXCK
SCK
Reference
VREFOUT
Timing Generator
ICLAMP DCK DCK HSOUT
Control
ACSIN
SYNC STRIPPER
DCSOUT
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PRODUCT SPECIFICATION
FMS9884A
Architectural Overview
Three separate digitizer channels are controlled by common timing signals derived from the Timing Generator. A/D clock signals can be derived from either a PLL or an external clock XCK. With the PLL selected, A/D clocks track the incoming horizontal sync signal connected to the HSIN input. Setup is controlled by registers that are accessible through the serial interface.
Output Data Configuration Output data number format for each channel is binary: 00 corresponds to the lowest input; FF corresponds to the highest input. Data can be released in either of two timing formats: 1. 2. Single 8-bit port at pixel rates up to 175Ms/s. Dual 8-bit ports, each running at half the conversion rate. Maximum rate is 88Ms/s per port. Data streams may be parallel or interleaved.
Conversion Channels
Typical RGB graphics signals, RIN, GIN, BIN are ground referenced with 700mV amplitude. If a sync signal is embedded then the usual format is sync on green with the sync tip at ground, the black level elevated to 300mV and peak green at 1000mV. AC coupled video signals must be level shifted to establish the lower level of the conversion range by clamping to the black level of the back porch (see Figure 1). Clamp pulses are derived from internal Timing and Control logic or from the external CLAMP input.
Timing and Control
Timing and Control logic encompasses the Timing Generator, PLL and Serial Interface. Timing Generator All internal clock and synchronization signals are generated by the Timing Generator. Master Clock source is either the PLL or the external clock input, XCK. Bit XCKSEL selects the Master Clock source. Two clocks are generated. Sampling clock, SCK is supplied to all three A/D converters. Phase of SCK can be adjusted in 32 11.25 degree phase increments using the 5-bit PHASE register. DCK is the output data clock. DCK and DCK are supplied as outputs for synchronizing data transfer from the digitizer outputs. Horizontal sync applied to the input, HSIN is propagated by the Timing and Control to the HSOUT output with a delay that aligns leading and trailing edges with the output data. Phase Locked Loop With a horizontal sync signal connected to the HSIN input pin, the PLL generates a high frequency internal clock signal, PXCK that is fed to the Timing and Control logic. Frequency of PXCK is set by the register programmable PLL divide ratio, PLLN. COAST is an input that disables the PLL lock to the horizontal sync input, HSIN. If HSIN is to be disregarded for a period such as the vertical sync interval, COAST allows the VCO frequency to be maintained. Omission of horizontal sync pulses during the vertical interval can cause tearing at the top of a picture, if COAST is not used. Two pixels per clock mode is set by programming the PLL to half the pixel rate. By toggling the INVCK pin between frames, even and odd pixels can be read on alternate frames. Serial Interface Registers are accessed through an I2C/SMBus compatible serial port. Four serial addresses are pin selectable.
RIN, GIN, BIN ICLAMP
Figure 1. Clamping to the back-porch
Gain and Offset Gain and Offset registers serve two functions: adjustment of contrast and brightness by setting RGB values in tandem; matching the gain and offsets between channels, by setting RGB values individually to obtain the same output levels. A/D conversion range can be matched to the amplitude of the incoming video signal by programming Gain Registers GR, GG and GB, which vary sensitivity (LSB/volt) over a 2:1 range. Incoming video signal amplitudes varying from 0.5 to 1.0 volt can be accommodated. Input offset voltage of each converter is programmable in 1 LSB steps through the 6-bit OSR, OSG and OSB registers. Range of adjustment is equivalent to -31 to +32 LSB. A/D Converter Each A/D converter digitizes the analog input into 8-bit data words. Latency is 5-61/2 clock cycles, depending upon the data out format. VREFIN is the source of reference voltage for the three A/D converters. VREFIN can be connected to either the internal bandgap voltage, VREFOUT or an external voltage.
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PRODUCT SPECIFICATION
Pin Assignments (128-Lead MQFP (KA) Package)
DRB0 DRB1 DRB2 DRB3 DRB4 DRB5 DRB6 DRB7 VDDO GND DGA0 DGA1 DGA2 DGA3 DGA4 DGA5 DGA6 DGA7 VDDO GND DGB0 DGB1 DGB2 DGB3 DGB4 DGB5 DGB6 DGB7 VDDO GND DBA0 DBA1 DBA2 DBA3 DBA4 DBA5 DBA6 DBA7 102 101 100 95 94 93 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 GND VDDO DRA7 DRA6 DRA5 DRA4 DRA3 DRA2 DRA1 DRA0 GND VDDO DCK DCK HSOUT DCSOUT GND VDDO GND GND GND VDDA PWRDN VREFOUT VREFIN VDDA 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
VDDO GND DBB0 DBB1 DBB2 DBB3 DBB4 DBB5 DBB6 DBB7 VDDO GND GND GND VDDP GND VDDP GND NC LPF XCK VDDP GND COAST HSIN GND
NC NC NC VDDA GND GND RIN VDDA GND VDDA VDDA GND GND ACSIN GIN VDDA GND VDDA VDDA GND GND BIN VDDA GND VDDA GND INVSCK CLAMP SDA SCL A0 A1 VDDP VDDP GND NC NC NC
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PRODUCT SPECIFICATION
FMS9884A
Pin Assignments
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name NC NC NC VDDA GND GND RIN VDDA GND VDDA VDDA GND GND ACSIN GIN VDDA GND VDDA VDDA GND GND BIN VDDA GND VDDA GND INVSCK CLAMP SDA SCL A0 A1 No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name VDDP VDDP GND NC NC NC GND HSIN COAST GND VDDP XCK LPF NC GND VDDP GND VDDP GND GND GND VDDO DBB7 DBB6 DBB5 DBB4 DBB3 DBB2 DBB1 DBB0 GND VDDO No. 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Name DBA7 DBA6 DBA5 DBA4 DBA3 DBA2 DBA1 DBA0 GND VDDO DGB7 DGB6 DGB5 DGB4 DGB3 DGB2 DGB1 DGB0 GND VDDO DGA7 DGA6 DGA5 DGA4 DGA3 DGA2 DGA1 DGA0 GND VDDO DRB7 DRB6 No. 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Name DRB5 DRB4 DRB3 DRB2 DRB1 DRB0 GND VDDO DRA7 DRA6 DRA5 DRA4 DRA3 DRA2 DRA1 DRA0 GND VDDO DCK DCK HSOUT DCSOUT GND VDDO GND GND GND VDDA PWRDN VREFOUT VREFIN VDDA
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PRODUCT SPECIFICATION
Pin Descriptions
Pin Name RIN, GIN, BIN DRA7-0 DRB7-0 DGA7-0 DGB7-0 DBA7-0 DBB7-0 CLAMP INVSCK Pin No. 7, 15, 22 105-112 95-102 85-92 75-82 65-72 55-62 28 27 Type/Value Input Output Output Output Output Output Output Input Input Pin Function Description Analog Inputs. Red Channel Port A Data Output. Full rate/half rate, interleaved/ parallel data depending upon selected mode. Red Channel Port B Data Output. Active for dual port mode only with interleaved/parallel outputs. High impedance when inactive. Green Channel Port A Data Output. See red channel port A. Green Channel Port B Data Output. See red channel port B. Blue Channel Port A Data Output. See red channel port A. Blue Channel Port B Data Output. See red channel port B. External Clamp Input. Invert Sampling Clock. Inverts SCK, the internal clock sampling the analog inputs. Supports Alternate Pixel Sampling mode for capture pixel rates up to 350Ms/s. External Clock input. Enabled if register bit, XCKSEL = H. Replaces PXCK clock generated by PLL. If unused, connect to ground through a 10k resistor. Output Data Clock. Clock for strobing output data to external logic. Output Data Clock Inverted. Inverted clock for strobing output data to external logic. Horizontal Sync Output. Reconstructed HSYNC delayed by FMS9884A latency and synchronized with DCK. Leading edge is synchronized to start of data output. Polarity is always active HIGH. Horizontal Sync input. Schmitt trigger threshold is 1.5V. A 5V source should be clamped at 3.3V or current limited to prevent overdriving ESD protection diodes. PLL Coast. Maintain frequency of PLL output clock PXCK, disregarding HSIN. If horizontal sync is missing during the vertical sync interval, PXCK clock frequency can be maintained by asserting COAST. PLL Low Pass Filter. Connect recommended PLL filter to LPF pin. (see Figure 19.) Analog Composite Sync Input. Input to sync stripper with 150mV threshold. Digital Composite Sync Output. Output from sync stripper. Bi-directional Serial Port Data. Bi-directional data. Input Input Input Input Serial Port Clock. Clock input. Address bit 0. Lower bit of serial port address. Address bit 1. Upper bit of serial port address. Power Down/Output Control. Powers down the FMS9884A and tri-states the outputs. Converter Channels
Timing Generator
XCK
44
Input
DCK DCK HSOUT
115 116 117
Output Output Output
Phase Locked Loop HSIN 40 Schmitt
COAST
41
Input
LPF Sync Stripper ACSIN DCSOUT Control SDA SCL A0 A1 PWRDN
45
Passive
14 118 29 30 31 32 125
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PRODUCT SPECIFICATION
FMS9884A
Pin Descriptions (Continued)
Pin Name Power and Ground VDDA VDDP VDDO GND 4, 8, 10, 11, 16, 18, 19, 23, 25, 124, 128 33,34,43,48,50 54, 64, 74, 84, 94, 104, 114, 120 5, 6, 9,12, 13, 17, 20, 21, 24, 26, 35, 39, 42, 47, 49, 51, 52, 53, 63, 73, 83, 93, 103, 113, 119, 121, 122, 123 127 126 ADC Supply Voltages. Provide a quiet noise free voltage. PLL Supply Voltage. Most sensitive supply voltage. Provide a very quiet noise free voltage. Digital Output Supply Voltage. Decouple judiciously to avoid propagation of switching noise. Ground. Returns for all power supplies. Connect ground pins to a solid ground plane. Pin No. Pin Function Description
VREFIN VREFOUT
Voltage Reference Input. Common reference input to RGB converters. Connect to VREFOUT, if internal reference is used. Voltage Reference Output. Internal band-gap reference output. Tie to ground through a 0.1F capacitor.
Addressable Memory
Register Map
Name PLLN11-4 PLLN3-0 Address 00 01 Function PLL divide ratio, MSBs. PLLN + 1 = total number of pixels per horixontal line. PLL divide ratio, LSBs. PLLN + 1 = total number of pixels per horizontal line. PLLN3-0 stored in the four upper register bits 7-4. PLLN3-0 GR7-0 GG7-0 GB7-0 OSR5-0 02 03 04 05 XXXX 80 80 80 80 Default (hex) 69 (1693) D0 (1693)
Gain, red channel. Adjustable from 70 to 140%. Gain, green channel. Adjustable from 70 to 140%. Gain, blue channel. Adjustable from 70 to 140%. Offset, red channel. OSR5-0 stored in the six upper register bits 7-2. Default value is decimal 32. OSR5-0 XX
OSG5-0
06
Offset, green channel. OSG5-0 stored in the six upper register bits 7-2. Default value is decimal 32. OSG5-0 XX
80
OSB5-0
07
Offset, blue channel. OSB5-0 stored in the six upper register bits 7-2. Default value is decimal 32. OSB5-0 XX
80
CD7-0 CW7-0 CONFIG1
08 09 0A
Clamp delay. Delay in pixels from trailing edge of horizontal sync. Clamp width. Width of clamp pulse in pixels. Configuration Register No. 1
80 80 F4
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FMS9884A
PRODUCT SPECIFICATION
Name PHASE7-0
Address 0B
Function Sampling clock phase. PHASE4-0 stored in upper register bits 7-3. PHASE sets the sampling clock phase in 11.25 increments. Default value is decimal 16. PHASE4-0 XXX
Default (hex) 80
PLLCTRL CONFIG2
0C 0D 0E 0F
PLL Control Configuration Reserved Reserved
24 00 0X 00
Register Definitions
Configuration Register 1 (0A)
Bit no. 0 1 Name XCKSEL Type R/W Description External Clock Select. Select internal clock source. 0: Internal PLL 1: XCK input. External Clamp Polarity. Select clamp polarity. 0: Active L. 1: Active H. External Clamp Select. Select clamp source. 0: Internally generated by PLL referenced to HSIN. 1: External CLAMP input. Coast Polarity. Select COAST input polarity. 0: Active L. 1: Active H. HSIN Polarity. Select horizontal sync input polarity. PLL is locked to selected edge: 0: Falling edge. 1: Rising edge. Output Data Format. Select format of data outputs. 0: Interleaved. DCK rising edge strobes port A data. DCK rising edge strobes port B data. 1: Parallel. Rising edge of DCK strobes port A and port B data. Output Data Porting. Data released at full rate through one port or through two half-rate ports. 0: Single 8-bit port. 1: Dual 8-bit ports.
2
XCLAMPOL
R/W
3
XCLAMP
R/W
4
COASTPOL
R/W
5
HSPOL
R/W
6
PARALLEL
R/W
7
DEMUX
R/W
PLL Configuration Register (0C)
Bit no. 1-0 4-2 Name -- IPUMP2-0 Type R/W Description Charge Pump Current. Selects Charge Pump current (A). (see Table 5. Charge Pump Current Codes) 000: 50 001: 100 010: 150 011: 250 100: 350 101: 500 110: 750 111: 1500 7
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PRODUCT SPECIFICATION
FMS9884A
Bit no. 6-5
Name FVCO1-0
Type R/W
Description VCO Frequency Range. Selects VCO frequency range (MHz). 00: 20-90 01: 20-90 10: 80-120 11: 110-175 Reserved. 0: Run. 1: (reserved).
7
--
R/W
Configuration Register 2 (0D)
Bit no. 0 3-1 4 Name -- REV OUTPHASE Type -- R R/W Description Reserved. Set to 0. Revision Number. Die revision number. Output Data Phase. In the dual port mode, selects either odd (1, 3, 5, ...) or even (2, 4, 6 ....) samples following the HSYNC leading edge to be emitted from Port 1. 0: Even samples to Port A, odd samples to Port B. 1: Odd samples to Port A, even samples to Port B. Reserved. Set to 00.
7-5
--
R/W
Test Register (0F)
Bit no. 7-0 Name -- Type R/W Description Reserved. After power-up, initialize this register with the default value 0x00. Register 0F does not respond with an acknowledge during serial bus access. Consequently, ACK remains H instead of being pulled H. Inputs are optimized for a source resistance of 37.5 to 75. To reduce noise sensitivity, the ultra-wide 500MHz input bandwidth may be reduced by adding a small series inductor prior to the 75 terminating resistor. See Applications Section.
Functional Description
There are two major sections within the FMS9884A Digitizer: 1. 2. Analog-to-digital Converter Channels, one for each channel, RGB and the voltage reference. Timing and Control comprising the PLL, Timing Generator, Sync Stripper and Serial Interface.
Clamps
If the incoming signals are not ground referenced, a clamp must be used to set the incoming video range relative to ground. Prior to each A/D converter, each channel includes a clamp that allows a capacitively coupled input to be referenced to the A/D converter bottom reference voltage when the clamp pulse is active. Source of the clamp signal is determined by the XCLAMP bit. Internal clamp timing is generated by the Timing and Control Block. Position and width of the internal clamp pulse, ICLAMP are programmable through registers CD and CW. External clamp input is selected by register bit XCLAMP and the external clamp polarity selected through register bit XCLAMPOL. To disable the clamp for DC coupled inputs, set XCLAMP = 1 with either of these conditions: 1. 2. XCLAMPOL = 0 with input CLAMP = H. XCLAMPOL = 1 with CLAMP = L.
A/D Converter Channels
Each of the three RGB channels consists of: 1. 2. 3. 4. A clamp to set the lower reference level of an AC coupled input. Gain and offset stages to tune the converter to input signal levels. An Analog-to-Digital Converter to digitize the analog input. A commutating switch for dual port operation.
Analog Inputs
Input signal range is 500 to 1000mV to support conversion of single-ended signals with a typical amplitude of 700mV p-p. With the clamp active, each input accommodates a negative 300mV excursion.
Best performance will be achieved with the clamp set active for most of the black signal level interval between the trailing edge of horizontal sync and the start of active video.
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FMS9884A
PRODUCT SPECIFICATION
Insufficient clamping can cause brightness changes at the top of the image and slow recovery from large changes in Average Picture Level (APL). Recommended value of CD is 0x10 to 0x20 for most standard video sources.
Offset is set through the Single-Ended to Differential Amplifier which translates the ground referenced input to a differential voltage centered around A/D common mode bias voltage. The 6-bit Offset D/A converter injects a current into RLEVEL with two components: 1. 2. IBIAS to establish the A/D common mode voltage. IOFFSET to set the offset from the common mode level.
Analog-to-Digital Converter
Figure 2 is a block diagram of the ADC core with gain and offset functions. G7-0, OS5-0, RGBIN and PD7-0 generically refer to the gain and offset register values, analog input and parallel data output of any RGB channel. Core of the ADC block is a high speed A/D encoder with differential inputs. Within the A/D converter core are the following elements: 1. 2. Differential track and hold. Differential analog-to-digital converter.
Voltage offset from the common mode voltage at the inverting input of the Track and Hold is:
255 + G 7-0 500 -* * V OS = ( OS 5-0 - 31 ) * ---------------------------- * -------255 255
Setting the gain register value G7-0 (GR7-0, GG7-0, GB7-0), establishes the gain D/A converter voltage which is the A/D reference voltage. Increasing video gain reduces the contrast of the picture since the number of output codes is reduced. Conversion range is defined by the gain setting according to Table 1.
Table 1. Gain Calibration
D/A converter gain tracks A/D gain with 1 LSB of offset corresponding to 1 LSB of gain. Increasing OSR5-0, OSG5-0, or OSB5-0 reduces brightness in the selected channel. Data output from the A/D converter is:
D 7-0 = S * V IN - ( OS 5-0 - 31 ) *
Impact of the offset values OSR5-0, OSG5-0, and OSB5-0 is shown in Table 2.
Table 2. Offset Calibration
G7-0 0 66h FFh
Conversion Range (mV) 500 700 1000
OS5-0 0 1Fh 3Fh
Output Offset (decimal) +31 0 -32
A/D Converter sensitivity is:
255 255 S = -------- * ---------------------------- LSB mV -* 500 255 + G 7 - 0
Sampling Clock PHASE Adjustment
Picture quality is strongly impacted by the PHASE4-0 value. If PHASE is not set correctly, any section of an image consisting of vertical lines may exhibit tearing.
VREF G7-0
Gain Register
D/A
Offset Register
OS5-0
Current D/A
IBIAS + IOFFSET A/D Core
RGBIN VOS RLEVEL Track & + Hold A/D D7-0
SCK
Figure 2. A/D Converter Architecture
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PRODUCT SPECIFICATION
FMS9884A
PHASE PXCK/XCK
SCK RINGINBIN DCK D7-0 RGBn
Figure 3. Internal Sampling Clock, SCK Timing
Figure 3 shows how an analog input, RINGINBIN is sampled by the rising edge of SCK after a delay PHASE from the rising edge of either PXCK or XCK. SCK can be delayed up to 32 steps in 11.25 increments by adjusting the register value, PHASE4-0. Output data, DCK and DCK are delayed in tandem with SCK relative to PXCK or XCK. There is a 5-51/2 clock latency between the data sample RGBn and the corresponding data out D7-0. Ideally, incoming pixels would be trapezoidal with fast risetimes and the sampling edge of the A/D clock, SCK would be positioned along the level section of the incoming pixel waveform as shown in Figure 4. There is a narrow zone of uncertainly where sampling during pixel rise time would cause an error in the value of the A/D data output, D7-0, which is shown as a value, 0-255.
Zones of Uncertainty RIN, GIN, BIN SCK
Zones of Serendipity
D7-0
Figure 5. Acceptable Pixel Sampling
RIN, GIN, BIN SCK
Referring to Figure 6, when the sample clock, SCK has some jitter, if the sampling edge occurs anywhere within the zone of uncertainty where the pixel rise time is steep, there will be amplitude modulation of the digitized data, D7-0, due to the sampling clock jitter. To avoid corruption of the image, setting the value PHASE7-0 is critical. PHASE4-0 should be trimmed to position the sampling edge of SCK within the zone of serendipity.
Zones of Uncertainty
D7-0
RIN, GIN, BIN
Figure 4. Ideal Pixel Sampling
SCK
In practice, high-resolution pixels have long rise-times. As shown in Figure 5, there are narrow zones of serendipity when the pixel amplitude is level. Samples are valid in these zones.
D7-0
Figure 6. Improper Pixel Sampling
Voltage References
An on-chip voltage reference is generated from a bandgap source. VREFOUT is the buffered output of this source that can be connected to VREFIN to supply a voltage reference that is common to the three converter channels. 10
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PRODUCT SPECIFICATION
VREFIN, with a nominal voltage of 1.25V, is the source of the differential reference voltages for each A/D converter. Reference voltages supplied to the differential inputs of the comparators in the A/D converters are derived from VREFIN.
1. 2. 3.
Single or dual output port. Interleaved or parallel output data. 1-pixel or 2-pixel.
Digital Data Outputs
Input horizontal sync, HSIN and outgoing data, D[7..0] are resynchronized to the delayed sample clock, SCK. Output timing characteristics are defined in Figure 7. Latency of the first pixel, N varies according to the mode:
Levels are 3.3 volt CMOS with the output supply variable between 2.5 and 3.3 V. PWRDN = L sets the outputs high-impedance. PWRDN = H enables the outputs.
HSIN PHASE N PXCK/XCK
SCK RGBIN DCK tDH DCK tDO D[7..0] D0 S0
HSOUT
Figure 7. Output Timing
Figures 13 through 21 depict data output timing relative to the sampling clock and inputs for all modes. Timing is referenced to the leading edge of HSIN when the first sample is taken at the rising edge of SCK. Status of register bit OUTPHASE, determines if even samples are directed the A-port and odd samples are directed to the B-port; or vice versa. Note the timing of the HSOUT waveform: 1. 2. 3. 4. 5. HSOUT is always active HIGH. Only the leading edge of HSOUT is active or selected by the HSPOL register bit. HSOUT is aligned with DCK. Trailing edge is linked to HSIN. If HSIN does not terminate before mid-line, HSOUT is forced low. A 50% duty cycle indicates that HSPOL is incorrectly set.
HS is the internal sync pulse generated from HSYNC. SCK is the internal A/D converter sampling clock. Output data transitions are synchronized with the falling edge of DCK. Output data should be strobed on the rising edge of DCK. A 5 to 6.5 clock cycle delay must be flushed before valid data is available.
Alternate Pixel Sampling Mode
A logic H on the CKINV pin inverts the sampling phase of SCK. In the Alternate Pixel Sampling Mode: 1. 2. PLL is run at half rate. SCK, DCK and DCK are half rate. CKINV is toggled between frames. (see Figure 18)
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PRODUCT SPECIFICATION
FMS9884A
O O O O O O O O O O O
E E E E E E E E E E E
O O O O O O O O O O O
E E E E E E E E E E E
O O O O O O O O O O O
E E E E E E E E E E E
O O O O O O O O O O O
E E E E E E E E E E E
O O O O O O O O O O O
E E E E E E E E E E E
O O O O O O O O O O O
E E E E E E E E E E E
O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2
Figure 8. Odd and Even Pixels in a Frame
Figure 10. Even Pixels from Frame 2
On one frame, even pixels are sampled. On the other, odd pixels are sampled. Alternate Pixel Sampling is similar to interlacing used in broadcast video, except that the columns of pixels are interlaced instead of lines.
O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
Figure 11. Combined Frames 1 and 2 Output.
Figure 9. Odd Pixels from Frame 1
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
Figure 12. Subsequent Output Combining Frames 2 and 3
RGBIN HSIN PXCK HS
P0
P1
P2
P3
P4
P5
P6
P7
5 PIPE DELAY SCK DATACK DA7-0 HSOUT D0 D1 D2 D3 D4 D5 D6 D7
Figure 13. Single Port Mode
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REV. 1.2.2 12/7/01
FMS9884A
PRODUCT SPECIFICATION
RGBIN HSIN PXCK HS SCK DATACK DA7-0 HSOUT
P0 P1 P2 P3 P4 P5 P6 P7
5 PIPE DELAY
D0
D2
D4
D6
Figure 14. Single Port Mode, Alternate Pixel Sampling, (Even Pixels)
RGBIN HSIN PXCK HS
P0 P1 P2 P3 P4 P5 P6 P7
5.5 PIPE DELAY SCK
DATACK DA7-0 HSOUT D1 D3 D5 D7
Figure 15. Single Port Mode, Alternate Pixel Sampling, (Odd Pixels)
RGBIN HSIN PXCK HS
P0
P1
P2
P3
P4
P5
P6
P7
5 PIPE DELAY SCK
DATACK DA7-0 DB7-0 HSOUT D0 D1 D2 D3 D4 D5 D6 D7
Figure 16. Dual Port Mode, Interleaved Outputs
REV. 1.2.2 12/7/01
13
PRODUCT SPECIFICATION
FMS9884A
RGBIN HSIN PXCK HS
P0
P1
P2
P3
P4
P5
P6
P7
6 PIPE DELAY SCK DATACK D0 DA7-0 HSOUT D1 D2 D3 D4 D5 D6 D7
Figure 17. Dual Port Mode, Parallel Outputs
RGBIN HSIN PXCK HS
P0 P1 P2 P3 P4 P5 P6 P7
5 PIPE DELAY SCK DATACK DA7-0 DB7-0 HSOUT D0 D2 D4 D6
Figure 18. Dual Port Mode, Interleaved Outputs, Alternate Pixel Sampling, (Even Pixels)
RGBIN HSIN PXCK HS
P0 P1 P2 P3 P4 P5 P6 P7
5.5 PIPE DELAY SCK DATACK DA7-0 DB7-0 HSOUT D1 D3 D5 D7
Figure 19. Dual Port Mode, Interleaved Outputs, Alternate Pixel Sampling, (Odd Pixels)
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REV. 1.2.2 12/7/01
FMS9884A RGBIN HSIN PXCK HS SCK DATACK DA7-0 DB7-0 HSOUT D0 D2 D4 D6 6 PIPE DELAY P0 P1 P2 P3 P4 P5 P6 P7
PRODUCT SPECIFICATION
Figure 20. Dual Port Mode, Parallel Outputs, Alternate Pixel Sampling, (Even Pixels)
RGBIN HSIN PXCK HS
P0 P1 P2 P3 P4 P5 P6 P7
6.5 PIPE DELAY SCK
DATACK DA7-0 DB7-0 HSOUT D1 D3 D5 D7
Figure 21. Dual Port Mode, Parallel Outputs, Alternate Pixel Sampling, (Odd Pixels)
Timing and Control
Timing and Control logic encompasses the PLL, Timing Generator and Sync Stripper.
The PLL consists of a phase comparator, charge pump VCO and /N counter, with the charge pump connected through the LPF pin to an external filter. These elements must be programmed to match the incoming video source to be captured. Values of IPUMP and FVCO for Standard VESA timing parameters are shown in Table 3. Timing of many computer video outputs does not comply with VESA recommendations. PLLN should be optimized to avoid vertical noise bars on the displayed image. Modes marked 2X are 2X-oversampled modes where the number of samples per horizontal line is doubled. To select this mode, the Phase-locked Loop Divide Ratio value must changed from PLL1x to:
PLL 2x = 2 * ( PLL 1x + 1 ) - 1
Phase Locked Loop
Two clock types originate in the PLL: 1. 2. Data clocks DCK and DCK. Internal sampling clock SCK.
DCK and DCK are used to strobe data from the FMS9884A to following digital circuits. SCK is the ADC sample clock which has adjustable phase controlled through the PHASE register. DCK and DCK are phase aligned with SCK. Reference for the PLL is the horizontal sync input, HSIN with polarity selected by the HSPOL bit. Frequency of the HSIN input is multiplied by the value PLLN + 1 derived from the PLLN11-4 and PLLN3-0 registers. PLLN + 1 should equal the number of pixels per horizontal line including active and blanked sections. Typically blanking is 20-30% of active pixels. Divide ratios from 2-4095 are supported. SCK, DCK and DCK run at a rate PLLN + 1 times the HSIN frequency.
REV. 1.2.2 12/7/01
Values of IPUMP and FVCO are set through the PLL Configuration Register (0x0C). Recommended external filter components are shown in Figure 22. RF Quality 10% ceramic capacitors with X7R dielectrc are recommended.
15
PRODUCT SPECIFICATION
FMS9884A
Table 3. Recommended IPUMP and FVCO values for Standard Display Formats
Standard VGA
Resolution 640 X 480
Refresh Rate 60 Hz 72 Hz 75 Hz 85 Hz 60 Hz 67 Hz 72 Hz 75 Hz 70 Hz 56 Hz 60 Hz 72 Hz 75 Hz 85 Hz 60 Hz 70 Hz 75 Hz 80 Hz 85 Hz 60 Hz 75 Hz 75 Hz 66 Hz 60 Hz 60 Hz 72 Hz 75 Hz 85 Hz 60 Hz 65 Hz 70 Hz 75 Hz 85 Hz
Horizontal Frequency 31.5 kHz 37.7 kHz 37.5 kHz 43.3 kHz 31.5 kHz 35 kHz 37.7 kHz 37.5 kHz 31.5 kHz 35.1 kHz 37.9 kHz 48.1 kHz 46.9 kHz 53.7 kHz 48.4 kHz 56.5 kHz 60.0 kHz 64.0 kHz 68.3 kHz 48 kHz 60 kHz 69 kHz 62 kHz 63 kHz 64.0 kHz 78.1 kHz 80.0 kHz 91.1 kHz 75.0 kHz 81.3 kHz 87.5 kHz 93.8 kHz 106.3 kHz
Sample Rate 25.175 MHz 31.500 MHz 31.500 MHz 36.000 MHz 50 MHz 31 MHz 63 MHz 72 MHz 56.6 MHz 36.000 MHz 40.000 MHz 50.000 MHz 49.500 MHz 56.250 MHz 65.000 MHz 75.000 MHz 78.750 MHz 85.500 MHz 94.500 MHz 64 MHz 80 MHz 100 MHz 93 MHz 108 MHz 108.000 MHz 135.000 MHz 135.000 MHz 157.500 MHz 162.000 MHz 175.500 MHz 189.000 MHz* 202.500 MHz* 229.500 MHz*
FVCO1-0 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 10
IPUMP2-0 100 100 100 100 100 100 100 100 100 100 100 110 110 111 111 111
2X
640 X 480
720 X 400 SVGA 800 X 600
XGA
1024 X 768
Mac
1024 X 768 1152 X 870
01 10 10 10 10 10 11 11 11 11 11
111 111 111 111 111 111 111 111 111 111 111
Sun HP SXGA
1152 X 900 1280 X 1024 1280 X 1024
UXGA
1600 X 1200
VESA Monitor Timing Standards and Guidelines, September 17, 1998 * Graphics sampled at 1/2 incoming pixel rate using Alternate Pixel Sampling mode.
VDDP C1 0.18F C2 0.018F
Loop performance is established by setting: 1. 2. 3. VCO frequency range through FVCO1-0. (see Table 4) Charge Pump Current through IPUMP2-0. (see Table 5) External loop filter component values.
R1 1.5K
LPF
Figure 22. Schematic, PLL Filter.
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REV. 1.2.2 12/7/01
FMS9884A
PRODUCT SPECIFICATION
Table 4. VCO Frequency Bands
FVCO2-0 Frequency Range (MHz) KVCO (MHz/V) 00 01 10 11 20-90 80-120 110-175 60 90 100
Operation of COAST is depicted in Figure 23. HSOUT polarity is always positive. When COAST = L, HSOUT tracks HSIN (shown with postive polarity in Figure 23): 1. 2. HSOUT rising edge tracks HSIN delayed by a few pixels. HSOUT falling edge tracks the trailing edge of HSIN with no delay.
Table 5. Charge Pump Current Levels
IPUMP2-0 000 001 010 011 100 101 110 111
Current (A) 50 100 150 250 350 500 750 1500
When COAST = H, the PLL flywheels, disregarding the incoming HSIN references, while the HSOUT waveform depends upon the state of HSIN. 1. If HSIN = H: a.) HSOUT rising edge remains locked to the PLL. b.) HSOUT trailing edge falls after 50% of the HSOUT period has expired. 2. HSIN transitions: a.) HSOUT rising edge remains locked to the PLL. b.) HSOUT falling edge is terminated by the trailing edge of HSIN. 3. If HSIN = L, then HSOUT = L
Setting SPHASE4-0 selects the sampling phase of SCK relative to PXCK in 32 steps of 11.25. Phase of the output data, DCK and DCK is slaved to the SCK phase. Clock jitter is less than 5% of pixel period in all operating modes. At lower frequencies below 40MHz, the jitter rises but can be reduced by over-sampling at a 2X clock rate. Data should be read out of one port using the dual port mode. See Performance section for jitter specifications and plots.
Timing Generator
Timing and Control logic generates: 1. 2. 3. 4. Internal sampling clock, SCK. Output data clocks, DCK and DCK. Output horizontal sync, HSOUT. Internal clamp pulse, ICLAMP.
COAST
COAST = H disables PLL lock to HSIN, while the VCO frequency is retained. VCO frequency remains stable over several lines without updates from HSIN. COAST can be connected directly to the vertical sync signal or supplied by the graphics controller.
With HSPOL set correctly, ICLAMP delay follows the trailing edge of horizontal sync in (HSIN). Delay is set by the CD register. Width of ICLAMP is set by the CW register. Range of CD and CW values is 1-255 pixels.
HSIN Trailing edge terminates HSOUT COAST
HSOUT
50% Timeout
Figure 23.
REV. 1.2.2 12/7/01
17
PRODUCT SPECIFICATION
FMS9884A
Sync Stripper
Some video signals include embedded composite sync rather than separate horizontal and vertical sync signals, typically sync on green. Composite sync is extracted from Composite Video at the ACSIN pin. When the ACSIN signal falls below a 150mV ground referenced threshold, sync is detected. Composite Sync Output, DCSOUT reflects the ACSIN sync timing with non-inverted CMOS digital levels.
Since the serial control port is design to interface with 3.3V logic, the pins must be protected by series connected 150 resistors if SDA and SCL signals originate from 5V logic. (See Applications Section)
Table 6. Serial Interface Address Codes
A1-0 00 01 10 11
7-bit Address 4C 4D 4E 4F
Power Down
PWRDN = L minimizes FMS9884A power consumption. Data outputs become high impedance. Clocks generation is stopped. Register contents are maintained. Sync stripping and the internal voltage reference function.
Serial Interface
Register access is via a 2-wire I2C/SMBus compatible interface. As a slave device, the 7-bit address is selected by the A1-0 pins (see Table 6). Serial port pins SDA and SCL communicate with the host SMBus/I2C controller which act as a master.
Two signals comprise the bus: clock (SCL) and bi-directional data (SDA). When receiving and transmitting data through the serial interface, the FMS9884A acts as a slave, responding only to commands by the I2C/SMBus master. Data received or transmitted on the SDA line must be stable for the duration of the positive-going SCL pulse. Data on SDA may change only when SCL = L. An SDA transition while SCL = H is interpreted as a start or stop signal.
SDA tBUFF tSTAH SCL tDAH tDHO tDAL tDSU tSTASU tSTOSU
Figure 24. Serial Bus: Read/Write Timing
SDA bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ACK
SCL
Figure 25. SerialBus: Typical Byte Transfer
SDA
A6
A5
A4
A3
A2
A1
A0
R/W\
ACK
SCL
Figure 26. Serial Bus: Slave Address with Read/Write Bit
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REV. 1.2.2 12/7/01
FMS9884A
PRODUCT SPECIFICATION
There are five steps within an I2C/SMBus cycle: 1. 2. 3. 4. 5. Start signal Slave address byte Pointer register address byte Data byte to read or write Stop signal
After the last read, there must be a stop cycle comprising a LOW-to-HIGH transition of SDA while SCL is HIGH. (see Figure 24, right waveform) A repeated start signal occurs when the master device driving the serial interface generates a start signal without first generating a stop signal to terminate the current communication. This is used to change the mode of communication (read, write) between the slave and master without releasing the serial interface lines.
When the Serial Bus interface is inactive, SCL = H and SDA = H. Communications are initiated by sending a start signal (Figure 24, left waveform) that is a HIGH-to-LOW transition on SDA while SCL is HIGH. A start signal alerts all slaved devices that a data transfer sequence is imminent. As shown in Figure 26, after a start signal, the first eight bits of data comprise a seven bit slave address followed a single R/W bit (Read = H, Write = L) to set the direction of data transfer: read from; or write to the slave device. If the transmitted slave address matches the address of the FMS9884A which set by the state of the ADD pin, the FMS9884A acknowledges by pulling SDA LOW on the 9th SCL pulse (see Figure 26). If the addresses do not match or the register being accessed is 0x0F, the FMS9884A does not acknowledge. For each byte of data read or written, the MSB is the first bit of the sequence.
Serial Interface Read/Write Examples
Examples below show how serial bus cycles can be linked together for multiple register read and write access cycles. For sequential register accesses, each ACK handshake initiates further SCL clock cycles from the master to transfer the next data byte. Write to one register 1. Start signal 2. Slave Address byte (R/W bit = LOW) 3. Pointer byte 4. Data byte to base address 5. Stop signal Write to four consecutive registers 1. Start signal 2. Slave Address byte (R/W bit = LOW) 3. Pointer byte 4. Data byte to base address 5. Data byte to (base address + 1) 6. Data byte to (base address + 2) 7. Data byte to (base address + 3) 8. Stop signal Read from one register 1. Start signal 2. Slave Address byte (R/W bit = LOW) 3. Pointer byte (= base address) 4. Stop signal (optional) 5. Start signal 6. Slave Address byte (R/W bit = HIGH) 7. Data byte from base address 8. Stop signal Read from four registers 1. Start signal 2. Slave Address byte (R/W bit = LOW) 3. Pointer byte (= base address) 4. Stop signal (optional) 5. Start signal 6. Slave Address byte (R/W bit = HIGH) 7. Data byte from base address 8. Data byte from (base address + 1) 9. Data byte from (base address + 2) 10. Data byte from (base address + 3) 11. Stop signal
Data Transfer via Serial Interface
If a slave device, such as the FMS9884A does not acknowledge the master device during a write sequence, SDA remains HIGH so the master can generate a stop signal. During a read sequence, if the master device does not acknowledge by bringing SDA = L, the FMS9884A interprets SDA = H as "end of data." SDA remains HIGH so the master can generate a stop signal (Figure 24, right waveform). To write data to a specific FMS9884A control register, three bytes are sent: 1. 2. 3. Write the slave address byte with bit R/W = L. Write the pointer byte. Write to the control register indexed by the pointer.
After each byte is written, the pointer auto-increments to allow multiple data byte transfers within one write cycle. Data is read from the control registers of the FMS9884A in a similar manner, except that two data transfer operations are required: 1. 2. 3. 4. Write the slave address byte with bit R/W = L. Write the pointer byte. Write the slave address byte with bit R/W = H Read the control register indexed by the pointer.
After each byte is read, the pointer auto-increments to allow multiple data byte transfers within one read cycle. Preceding each slave write, there must be a start cycle. Following the pointer byte there should be a stop cycle.
REV. 1.2.2 12/7/01
19
PRODUCT SPECIFICATION
FMS9884A
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Power Supply Voltages VCC (Measured to GND) Digital Inputs Applied voltage (Measured to GND)2 Forced current
3, 4
Min. -0.5 -0.3 -5.0 -0.5 -10.0 -0.5 -6.0 -8.0
Typ.
Max. 4 VDDA 5.0 VDDA 10.0
Unit V V mA V mA V
Analog Inputs Applied Voltage (Measured to GND)2 Forced current3, 4 Digital Outputs Applied voltage (Measured to GND)2 Forced current3, 4 Forced current3, 4 Short circuit duration (single output in HIGH state to ground) Temperature Junction Lead Soldering (10 seconds) Vapor Phase Soldering (1 minute) Storage Electrostatic Discharge5 -65 150 300 220 150 150 C C C C V 6.0 8.0 1 mA mA second
Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. 5. EIAJ test method.
Operating Conditions
Parameter VDDA VDDP VDDO TA ADC Power Supply Voltage PLL Power Supply Voltage Output Power Supply Voltage Ambient Temperature, Still Air A/D analog input range, min. A/D analog input range, max. 1000 140 Ms/s > 140 Ms/s Min. 3.0 3.0 3.4 2.2 0 Nom. 3.3 3.3 3.5 2.5-3.3 Max. 3.6 3.6 3.6 3.6 70 500 Units V V V V C mV p-p mV p-p
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REV. 1.2.2 12/7/01
FMS9884A
PRODUCT SPECIFICATION
Electrical Characteristics1
Parameter Power Supply Currents IDDA IDDD IDDP PD IPD PDD CI CO IIH IIL VIH VIL IOHD IOHC IOLD IOLC VOH VOL VSMIH VSMIL VSMOL ISMOH ISMOL IB EOS Supply current, ADC Supply current , Digital Output Supply current, PLL Power dissipation Power-down current Powered-down disspation Input Capacitance Output Capacitance Input Current, HIGH Input Current, LOW Input Voltage, HIGH Input Voltage, LOW Output Current, HIGH, data Output Current, HIGH, clock Output Current, LOW, data Output Current, LOW, clock Output Voltage, HIGH Output Voltage, LOW (VDD3) Input Voltage, HIGH Input Voltage, LOW Output Voltage, LOW Output Current, HIGH (Open Drain) Output Current, LOW Input bias current Input Offset Voltage3
2
Conditions Operating, 25C Operating, 25C Operating, 25C 0 to 70C 0 to 70C 0 to 70C 25C 25C 0 to 70C 0 to 70C 0 to 70C 0 to 70C 0 to 70C 0 to 70C 0 to 70C 0 to 70C IOH = max., 0 to 70C IOL = max., 0 to 70C 0 to 70C 0 to 70C ISMOL = max. 0 to 70C 0 to 70C 0 to 70C 0 to 70C 0 to 70C 0 to 70C
Min.
Typ. Max. 210 30 50 15 50 3 7 270 40 65 20 70
Unit mA mA mA mW mA mW pF pF
950 1300
Digital Inputs/Outputs
-1 -1 2.5
+1 +1 0.8 4 8 4 8
A A V V mA mA mA mA V
VDDO-0.1 0.1 2.5 0.8 0.1 -1 4 -1 11 1.15 1.25 1.35 50 1 +1
V V V V A mA A mV V ppm/C
Serial Bus I/O
Analog Inputs
Reference Output Output Voltage Temperature Coefficient
Notes: 1. Unless otherwise stated, 0 to 70C 2. DEMUX = 1; DCK, DCK load = 15 pF; data load = 5 pF. 3. For optimum performance, null the input offset by calibrating gain and offset (see Firmware section under Applications Information).
REV. 1.2.2 12/7/01
21
PRODUCT SPECIFICATION
FMS9884A
Switching Characteristics
Parameter Analog-to-Digital Converters Conversion rate tSKEW Data to clock skew HSIN input frequency Maximum PLL clock rate FMS9884AKAC100 FMS9884AKAC140 FMS9884AKAC175 Minimum PLL clock rate Serial Bus Interface tDAL tDAH tSTAH tSTASU tSTOSU tBUFF tDSU tDHO SCL Pulse Width, LOW SCL Pulse Width, HIGH SDA Start Hold Time SCL to SDA Setup Time (Start) SCL to SDA Setup Time (Stop) SDA Stop Hold Time Setup SDA to SCL Data Setup Time SDA to SCL Data Hold Time 0 to 70C 0 to 70C 0 to 70C 0 to 70C 0 to 70C 0 to 70C 0 to 70C 0 to 70C 4.7 4.0 4.0 4.7 4.0 4.7 250 0 s s s s s s ns ns 0 to 70C Timing Generator 0 to 70C 0 to 70C 15 108 140 175 20 MHz 110 kHz MHz 0 to 70C 0 to 70C 10 -0.5 175 2.0 Ms/s ns Conditions Min. Typ. Max. Unit
System Performance Characteristics
Parameter Analog to Digital Converter ELI ELD Integral Linearity Error1 Differential Linearity Missing Codes Input full scale matching Offset adjustment range Gain tempco BW tOV tPP Analog bandwidth, full power Transient response Over-voltage recovery time Peak-to-peak PLL Jitter @ MHz 25.175 31.5 40 49.5 78.75 108 135 162 175 22 Phase Locked Loop 25C 6.5 4.1 3.3 2.3 1.5 1.0 0.8 0.7 0.8
REV. 1.2.2 12/7/01
Conditions 0 to 70C 0 to 70C 0 to 70C 0 to 70C 0 to 70C 25C 25C 25C 25C
Min. -2.5 -1.0
Typ.
Max. 2.5 +1.0 0
Unit LSB LSB %FS2 %FS2 ppm/C MHz ns ns ns
Error1
2 22 23.5 280 500 2 1.5
6 25
FMS9884A
PRODUCT SPECIFICATION
System Performance Characteristics (continued)
Parameter Thermal JC JA Resistance, junction-to-case Resistance, junction-to-ambient 8.4 35 C/W C/W Conditions Min. Typ. Max. Unit
Notes: 1. Calibrated to 700 mV input. 2. Percentage of Full Scale (uncalibrated).
7 6 5 Jitter (ns p-p) 4 3 2 1 0
0
20
40
60
80
100
120
140
160
180
200
Pixel Clock (MHz)
Figure 27. Pixel Clock Jitter vs. Frequency
Applications Information
Two applications circuits are reviewed: 1. AC coupled digitizer with clamp. 2. AC coupled digitizer with dual ported outputs and sync stripping. To minimize component count, use of the following on-chip circuits is recommended: 1. ADC sampling clock. 2. Clamp. 3. Voltage reference 4. Dual ported data outputs Optimum PLL Configuration Register (address 0x0C) settings for typical graphics modes are listed in Table 3. Unless otherwise indicated, all modes are compliant with VESA specifications. For unlisted modes, values should be adjusted to optimize performance. By adjusting the values in the gain (GR, GG, GB) and offset (OSR, OSG, OSB) registers, the input conversion range can be matched to the incoming analog signals. To use the FMS9884A in applications where the PLL clock frequency will exceed 140 MHz, the PLL power supply voltage must be 3.4 V min. For applications up to and including 140 MHz, the PLL supply can be 3.0 V min.
REV. 1.2.2 12/7/01
AC Coupled Digitizer
Shown in Figure 28 is an implementation of a video digitizer with AC coupled RGB inputs. Horizontal sync input, HS is passed through a voltage divider which attenuates the 5.0 V logic HIGH excursion to the 3.3 V HIGH input level of the FMS9884A. Vertical sync is also attenuated to make the VSOUT level compatible with 3.3 V pixel processing following the FMS9884A. Output data is three channel port A data only with a maximum rate of 175Ms/s 24-bit pixels. Data is clocked out on the negative edge of DCK. HSOUT defines the active video along a line, while incoming vertical sync, VSIN is propagated as VSOUT to the output data to synchronize handling of digitized frames of output data. Control is through the serial port with 150 resistors inserted to allow interfacing with 5V logic. If the serial bus is operates with 3.3V levels, these resistors are unnecessary.
23
PRODUCT SPECIFICATION
FMS9884A
J1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SVGA R5 1K RED GREEN BLUE
C1 .047F C2 0.18F R1 75
VDDP
VDDA
VDDO
4 8 10 11 16 18 19 23 25 124 128 VD VD VD VD VD VD VD VD VD VD VD
AD9884 C6 0.018F R2 1.5K 33 34 43 48 50 7 15 22 27 28 40 41 R7 1.8K 44 45 29 30 PVD PVD PVD PVD PVD RIN GIN BIN CLKINV CLAMP HSIN COAST CKEXT FILT SDA SCL A0 A1 ACSIN NC1 NC2 NC3 NC4 NC5 NC6 NC7 REFIN DATACK DATACK HSOUT PWRDN
54 VDD VDD 64 74 VDD 84 VDD VDD 94 104 VDD VDD 114 VDD 120
C4 .047F
U1
C7 .047F R3 75
HS VSIN 75 R4
DB _ B7 DB _ B6 DB _ B5 DB _ B4 DB _ B3 DB _ B2 D B_ B1 DB _ B0 DB _ A7 DB _ A6 DB _ A5 DB _ A4 DB _ A3 DB _ A2 DB _ A1 DB _ A0 DG_ B7 DG_ B6 DG_ B5 DG_ B4 DG_ B3 DG_ B2 DG_ B1 DG_ B0 DG_ A7 DG_ A6 DG_ A5 DG_ A4 DG_ A3 DG_ A2 DG_ A1 DG_ A0 DR_B7 DR_B6 DR_B5 DR_B4 DR_B3 DR_B2 DR_B1 DR_B0 DR_A7 DR_A6 DR_A5 DR_A4 DR_A3 DR_A2 DR_A1 DR_A0 DCSOUT
55 56 57 58 59 60 61 62 BA [ 7..0] 65 66 67 68 69 70 71 72 75 76 77 78 79 80 81 82 85 86 87 88 89 90 91 92 95 96 97 98 99 100 101 102 105 106 107 108 109 110 111 112 118 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 GA7 GA6 GA5 GA4 GA3 GA2 GA1 GA0 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0
R6 1K
R10 150 SDA SCL R11 150 R8 1.8K
GA[7 ..0]
31 32 14 1 2 3 36 37 38 46 R9 10K 127 115 116 117 125 126
VDD
RA[7 ..0]
REFOUT
C19 0. F 1
5 6 9 12 13 17 20 21 24 26 35 39 42 47 49 51 52 53 63 73 83 93 103 11 3 11 9 12 1 12 2 12 3
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
DCK HSOUT VSOUT
Figure 28. Schematic, VGA Digitizer, Single-Port Outputs
VGA Source with Dual Ported Outputs
Shown in Figure 29 is a more complex implementation of a video digitizer. Incoming RGB video has sync-on-green. Output data is dual ported. COAST is shown to free wheel the PLL when horizontal sync is inactive or 2H pulse are present. RGB inputs signals are AC coupled to the FMS9884A RGB inputs with the green input connected to the Sync Separator input, CVIN. Output data is three channel dual port data with a maximum rate of 70Ms/s per port. Port A data is synchronzed to the negative edge of DCK. Port B data transitions on: 1. 2. Positive edge of DCK in the Parallel Data Out Mode. Negative edge of DCK in the Interleaved Data Out Mode.
DCK and DCK clocks should be timed to strobe data that is valid between transitions. Composite Sync from the Sync Stripper output CSOUT is supplied to the HSYNC input as a reference for the internal PLL. CSSOUT contains horizontal and vertical sync signals that can be extracted by subsequent Sync processing logic. If the vertical sync pulse omits horizontal sync or if serrations or equalizing pulses are present, then the sync processing logic should emit a COAST signal to disengage the PLL from the HSYNC input during the Vertical Sync interval. Vertical and horizontal sync waveforms within CSSOUT signal frame the active video area.
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FMS9884A
PRODUCT SPECIFICATION
J1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SVGA RED GREEN BLUE C5 .047F
C1 .047F
VPLL
VADC
VDD
4 8 10 11 16 18 19 23 25 124 128
R1 75
AD9884 R2 1.5K C4 0.018F 33 34 43 48 50 7 15 22 27 28 40 PVD PVD PVD PVD PVD RIN GIN BIN CLKINV CLAMP HSIN COAST CKEXT FILT SDA SCL A0 A1 ACSIN NC1 NC2 NC3 NC4 NC5 NC6 NC7 REFIN DATACK DATACK HSOUT PWRDN
54 64 74 84 94 104 114 120
C3 .047F
C2 0.18F
U1 BB [ 7..0]
DV DV DV DV DV DV DV DV DV DV DV
DDV DDV DDV DDV DDV DDV DDV DDV
R4 75
R3 75
DB _ B7 DB _ B6 DB _ B5 DB _ B4 DB _ B3 DB _ B2 D B_ B1 DB _ B0 DB _ A7 DB _ A6 DB _ A5 DB _ A4 DB _ A3 DB _ A2 DB _ A1 DB _ A0 DG_ B7 DG_ B6 DG_ B5 DG_ B4 DG_ B3 DG_ B2 DG_ B1 DG_ B0 DG_ A7 DG_ A6 DG_ A5 DG_ A4 DG_ A3 DG_ A2 DG_ A1 DG_ A0 DR_B7 DR_B6 DR_B5 DR_B4 DR_B3 DR_B2 DR_B1 DR_B0 DR_A7 DR_A6 DR_A5 DR_A4 DR_A3 DR_A2 DR_A1 DR_A0 DCSOUT
55 56 57 58 59 60 61 62 65 66 67 68 69 70 71 72 75 76 77 78 79 80 81 82 85 86 87 88 89 90 91 92 95 96 97 98 99 100 101 102 105 106 107 108 109 110 111 112 118
BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 GB7 GB6 GB5 GB4 GB3 GB2 GB1 GB0 GA7 GA6 GA5 GA4 GA3 GA2 GA1 GA0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
BA [7..0]
GB[7 ..0]
COAST
41 44
PWRDN\ SDA SCL
45 29 30 31 32 14 1 2 3 36 37 38 46 127 115 116 117 125 126
GA[7 ..0]
RB[7 ..0]
RA[7 ..0]
REFOUT
C17 0. F 1
5 6 9 12 13 17 20 21 24 26 35 39 42 47 49 51 52 53 63 73 83 93 103 11 3 11 9 12 1 12 2 12 3
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
DCK DCK \ HSOUT
Figure 29. Schematic, VGA Digitizer, Dual Port Outputs
Printed Wiring Board Design Guidelines
Recommended strategy is to mount the FMS9884A over a ground plane with carefully routed analog inputs and digital outputs. All connections should be treated as transmission lines to ensure that reflections due to mismatches are minimized and ground return currents do not interfere with critical signals. Analog Inputs Recommendations: 1. 2. Keep analog trace lengths short to minimize crosstalk. Terminate analog inputs with 75 resistors, placed close to the FMS9884A analog inputs, RIN, GIN and BIN. By matching transmission line impedances, reflections will be minimized.
3. 4.
Layout traces as 75 transmission lines. Avoid running analog traces near digital traces. Due to the wide input bandwidth (500MHz) digital noise can easily leak into analog inputs. If necessary, limit bandwidth by adding a ferrite bead in series with each RGB input as shown in Figure 30. A Fair-Rite #2508051217Z0 is recommended. Further bandwidth reduction using a shunt 10pF capacitor may reduce snow (intensity noise) caused by HF noise riding on the RGB input. Mismatches, reflections and noise may cause ringing or distortion of the incoming video signals. Locate the PLL filter clear of other signals.
5.
6.
REV. 1.2.2 12/7/01
25
PRODUCT SPECIFICATION
FMS9884A
7.
Bypass the reference with a 0.1F capacitor to ground.
L1 BEAD R, G, B INPUT R1 75 C1 47nF RIN, GIN, BIN C2 10pF
5. 6. 7.
If necessary terminate the HSIN input with 330/220. If necessary, to reduce reflections, EMI or spikes add a 50-200 resistor at each data output pin. To minimize noise within the FMS9884A, restrict the capacitive load at the digital outputs to < 10pF.
Figure 30. RGB Input Filter Options
Power and Ground A schematic of the recommended power distribution is shown in Figure 31. Note that: 1. 2. Analog and digital circuits are layed out over a common solid ground plane. Each FMS9884A pin is decoupled with a 0.1F capacitor. A group of pins may be de-coupled through a common capacitor if no pin is more than 5 mm from the capacitor. A separate regulated supply is used for the phase-locked loop power supply, VDDP. Capacitors are attached to each PLL pin or pin-pair.
Digital I/O Recommendations: 1. 2. 3. 4. Route digital I/O signals clear of analog inputs. Terminate clock lines to reduce reflections. Treat clock lines as transmission lines. Scale the HSIN input to 3.3V, using a resistor network or a series 1 k resistor. Limit Serial Port inputs SDA and SDL with 150 resistors connected directly to the pins.
3. 4. 5.
Pins 33, 34 C2 0.01F
VPLL
L1 BEAD
U3 RC1117-3.3 2 OUT 4 OUT IN ADJ/GND 1 3 C1 0.1F
Pin 43 C3 0.1F
Pin 48 C4 0.01F
U2 RC1117-3.3 2 OUT 4 OUT IN ADJ/GND 1 L2 BEAD 3 C7 0.1F Power Input + C8 10F
Pin 50 C5 0.1F + C6 10 F
VADC Pins C10 C11 C12 C13 C14 C15 C16 C17 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F
+ C26 10F U3 RC1117-3.3 2 OUT 3 ADJ/GND IN 4 OUT + C25 10F 1 C9 0.1F
VDD Pins C18 C19 C20 C21 C22 C23 C24 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F
L3 BEAD
Figure 31. Recommended Power Distribution
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REV. 1.2.2 12/7/01
FMS9884A
PRODUCT SPECIFICATION
Physical placement of PLL power supply decoupling components is critical. Bearing in mind the following suggestions: 1. 2. 3. All components should be placed in close proximity to the FMS9884A pins. Routing through vias should be avoided, if possible. Each VDDP/GND pin pair: 33&34/35, 43/42, 48/47, and 50/49 should be decoupled with a 100-1000p/10F pair of capacitors (see Figure 31). If board space is limited, use as many capacitor pairs as possible. Use Fair-rite 274 301 9447 bead.
Firmware
Best performance can be achieved by correctly setting the FMS9884A registers. Here are some recommendations: 1. Set the value of PLLN equal to the number of pixels to be sampled minus one. With this setting, the number of samples per horizontal line equals the number of pixels. If PLLN + 1 does not equal the number of pixels, there will be irregular intensities on text and an interference pattern on a vertical grill pattern. Calibrate Offset and Gain by first setting each input to 0mV. Then adjust OSR, OSG, and OSB to set each RGB data output D7-0 = 0x00. Next with 700mV input, adjust GR, GG and GB so that each RGB data output D7-0 = (same value), typically 240 decimal. Clamp registers, CD and CW, should be programmed to maximize the period of the clamp during the backporch, while not encroaching into the sync or active video periods. PHASE must be trimmed to minimize onscreen snow (intensity noise) when a vertical grill pattern is displayed. FVCO must be set to encompass the incoming frequency range. IPUMP must be set to minimize intensity noise. To ensure correct power-on defaults, program all registers including Test Register 0x0F, which must be set to 0x00 for normal operation. Note that unlike registers 0x00 through 0x0D, register 0x0F does not acknowledge. The ACK bit remains H instead of being pulled L.
4.
2.
3.
4. 5. 6. 7.
REV. 1.2.2 12/7/01
27
PRODUCT SPECIFICATION
FMS9884A
Mechanical Dimensions
128-Lead MQFP (KA) Package
Symbol Min. A A1 A2 D D1 D2 E E1 E2 L N e b ccc 0.65 -- 0.25 2.57 Millimeters Typ. 3.04 0.33 2.71 22.60 BSC 20.00 BSC 18.00 BSC 17.20 BSC 14.00 BSC 12.00 BSC 0.70 128 0.50 BSC -- 0.12 E E1 2 E2 .40 Min. e 0 Min. 0.13 R Min. Datum Plane .13/.30 R Max 3.40 -- 2.87 Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1994. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.254mm per side. 3. "N" is the number of terminals. 3, 5 4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm in excess of the "b" dimension at the maximum material condition.
0.95
4
0.13
0.28
D2 D1/2 D
L 1.60 Ref. Lead Detail
0-7
A2 A A1 B Seating Plane
See Lead Detail Base Plane -CLEAD COPLANARITY ccc C
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REV. 1.2.2 12/7/01
PRODUCT SPECIFICATION
FMS9884A
Ordering Information
Product Number FMS9884AKAC100 FMS9884AKAC140 FMS9884AKAC175 Temperature Range 0C to 70C Screening Commercial Package 128 Lead MQFP Package Marking 9884AKAC100 9884AKAC140 9884AKAC175
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
12/7/01 0.0m 006 Stock#DS30009884 2001 Fairchild Semiconductor Corporation

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